Total 27 technology development job vacancies in Engineering category in Bengaluru

We are looking for an experienced Oracle PL/SQL and Python Developer to join our team. The ideal candidate will have 6+ years of hands-on experience, proficient in Oracle PL/SQL development and Python scripting.

Responsibilities:

1. Database Development: Design, develop, and optimize Oracle PL/SQL stored procedures, functions, and triggers. Create and maintain efficient and scalable database structures.
2. Python Scripting: Develop Python scripts for automation, data manipulation, and integration. Integrate Python scripts with Oracle databases and other systems.
3. Data Migration and Integration: Design and implement data migration scripts. Integrate databases with external systems using both PL/SQL and Python.
4. Performance Optimization: Analyze and optimize SQL queries, PL/SQL, and Python scripts for performance.
5. Collaboration: Work with cross-functional teams, providing technical support and expertise.

• New Product Development Design to update all DMR documents by using NX and Solid Works
• Handling Injection molding plastic components design for medical consumable products.
• Set up project Templets in the PLM System
• To support LCM DMR topics in PLM
• To prepare project stage reviews from the documents side
• Hands on experience in Plastics designs and plastic materials
• Injection molding process
• Concept development
• Should be good mechanical design calculations.
• Minimum of 2 years hands-on experience in NX / (UG NX) is must.

The FPGA design team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital.

 Your main responsibilities as part of a winning group:

• Complex logic blocks & IPs design
• Work in a multi-disciplinary environment with a variety of complex interfaces.

1. Development of ASIC verification and Validation plans
2. Development of C/UVM tests for ASIC verification and validation to achieve comprehensive coverage
3. Working with ASIC design and architecture teams to understand functionality of logic blocks of SSD controller
4. Comprehending ＂big picture＂ at the ASIC architectural and system level as well as executing at the detail block level.

Western Digital reliance on software development workflows is growing by leaps and bounds as a leading provider of Storage Solutions.  As Secure Development Factory (SDF) Agile Tools Engineer, you will be at the heart of Western Digital’s engineering process, delivering the software development tools and infrastructure that empowers engineering teams to develop and deliver high quality products quickly. The sheer diversity of Western Digital’s products demands a secure development infrastructure that allows teams to develop many types of software at scale without sacrificing security, development velocity, stability, code quality or code health.  

This position requires partnering with global WDC engineering teams, IT teams and others to deliver the right scalable tools and infrastructure that help engineers develop, test, debug and release software and products quickly. We impact thousands of Western Digital developers worldwide and millions of customers by increasing the pace of product development, improving product quality and directly impacting WDC’s bottom line.

The ideal candidate will have a passion for technology, a relentless focus on the customer experience and an ability to multitask, assimilate data, make decisions and prioritize complex work while paying attention to the details.  Communication with internal customers, vendors and co-workers in a clear and professional manner is an absolute must.

What you will be doing:

• For the Engineering Services Agile Tools team, we are looking for a senior Agile Tools Solutions engineer to deploy, support, develop, maintain and troubleshoot the Atlassian Agile tools development solutions such as
  • JIRA / JIRA Datacenter
  • Confluence
  • BitBucket / Bitbucket Datacenter
  • Groovy Scripting
  • Ansible automation
• Work with development teams to on-board them and their environments into the Secure Development Factory Atlassian environments to optimise Western Digital’s Engineering Services provided to development teams and their workflows.
• Manage large scale Jira/Bitbucket/Confluence migration on-prem as well as to Atlassian SaaS
• Expertise in handling custom workflow design, automation, Atlassian product license management
• Knowledge on Atlassian SaaS migrations - from on-prem to Cloud migration.
• Good experience building and maintaining Atlassian instance supporting 15K+ users.
• Experience handling consolidation of multiple Atlassian instance into single deployment and handling conflicts with zero downtime & application availability impact
• Lead discussion with various stakeholders to understand the requirements, drive implementation and coordinate evaluation
• Subject matter expert for all Atlassian products with good troubleshooting skills to fix production issues single headedly.
• Skillset to conduct periodic security audit, monitor Atlassian deployments using various monitoring solutions like Prometheus, Grafana, Icinga etc.
• Work closely with development teams (development, release, QA, production) to constantly look for ways to bring out new solutions and improve already solutions deployed to meet their needs.

Western Digital reliance on software development workflows is growing by leaps and bounds as a leading provider of Storage Solutions.  As Secure Development Factory (SDF) Agile Tools Engineer, you will be at the heart of Western Digital’s engineering process, delivering the software development tools and infrastructure that empowers engineering teams to develop and deliver high quality products quickly. The sheer diversity of Western Digital’s products demands a secure development infrastructure that allows teams to develop many types of software at scale without sacrificing security, development velocity, stability, code quality or code health.  

This position requires partnering with global WDC engineering teams, IT teams and others to deliver the right scalable tools and infrastructure that help engineers develop, test, debug and release software and products quickly. We impact thousands of Western Digital developers worldwide and millions of customers by increasing the pace of product development, improving product quality and directly impacting WDC’s bottom line.

The ideal candidate will have a passion for technology, a relentless focus on the customer experience and an ability to multitask, assimilate data, make decisions and prioritize complex work while paying attention to the details.  Communication with internal customers, vendors and co-workers in a clear and professional manner is an absolute must.

What you will be doing:

• For the Engineering Services Agile Tools team, we are looking for a senior Agile Tools Solutions engineer to deploy, support, develop, maintain and troubleshoot the Atlassian Agile tools development solutions such as
  • JIRA / JIRA Datacenter
  • Confluence
  • BitBucket / Bitbucket Datacenter
  • Groovy Scripting
  • Ansible automation
• Work with development teams to on-board them and their environments into the Secure Development Factory Atlassian environments to optimise Western Digital’s Engineering Services provided to development teams and their workflows.
• Manage large scale Jira/Bitbucket/Confluence migration on-prem as well as to Atlassian SaaS
• Expertise in handling custom workflow design, automation, Atlassian product license management
• Knowledge on Atlassian SaaS migrations - from on-prem to Cloud migration.
• Good experience building and maintaining Atlassian instance supporting 15K+ users.
• Experience handling consolidation of multiple Atlassian instance into single deployment and handling conflicts with zero downtime & application availability impact
• Lead discussion with various stakeholders to understand the requirements, drive implementation and coordinate evaluation
• Subject matter expert for all Atlassian products with good troubleshooting skills to fix production issues single headedly.
• Skillset to conduct periodic security audit, monitor Atlassian deployments using various monitoring solutions like Prometheus, Grafana, Icinga etc.
• Work closely with development teams (development, release, QA, production) to constantly look for ways to bring out new solutions and improve already solutions deployed to meet their needs.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. As part of the CAD team our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams' activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today.

What you will be doing:

• Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques.

• Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.

• Support development of tools using C++/Python/TCL.

• Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.

What we need to see:

• Smart, diligent and motivated to work in our CAD group.

• BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience.

• 8+ years of relevant work experience.

• Knowledge or experience with DFT, DFP is a plus.

• Familiar with Verilog and ASIC design principles, including knowledge of logic cells.

• Software engineering: software design, algorithms, and QA.

• Strong C++ programming experience.

• Solid programming and scripting skills in Python or TCL desired.

• Having strong interpersonal skills will serve you well in this role.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. As part of the CAD team our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams' activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today.

What you will be doing:

• Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques.

• Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.

• Support development of tools using C++/Python/TCL.

• Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.

What we need to see:

• Smart, diligent and motivated to work in our CAD group.

• A BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience.

• 8+ years of relevant work experience.

• Knowledge or experience with DFT, DFP is a plus.

• Familiar with Verilog and ASIC design principles, including knowledge of logic cells.

• Software engineering: software design, algorithms, and QA.

• Strong C++ programming experience.

• Solid programming and scripting skills in Python or TCL desired.

• Having strong interpersonal skills will serve you well in this role.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you!

Flowserve is a world-leading manufacturer and aftermarket service provider of comprehensive flow control systems. Driven by our Purpose, we are committed to building a more sustainable future to make the world better for everyone. With more than 16,000 employees in more than 50 countries, we combine our global reach with local presence. We support more than 10,000 customers worldwide, creating products to meet the needs of our customers who are supplying energy, fresh water, pharmaceuticals and other essentials to consumers, businesses and governments globally.

Join a company where the people challenge themselves to approach each situation with ingenuity and creativity to help provide our customers with the most innovative flow control products and services. You will be part of a team known for its industry-leading talent, unparalleled portfolio, and unmatched commitment to customer success. Flowserve’s culture promotes recognition and rewards creativity, hard work, and commitment. We invite you to put your talents and career in motion at Flowserve.

Role Summary

In this role you will report into the Supervisor, Engineering. You will be part of an exciting new team and be involved in application design, developing real-time embedded firmware for microcontrollers and designing to meet the requirements of functional safety standards.

Responsibilities

• Low-power electronics firmware development

• Applications design that communicates with peripheral components such as A/Ds, DAC, UARTs, flash memories, I2C, RS- 232/ 485 and EEPROMS, Character LCD, Graphic LCD, RFID, BLUETOOTH, PWMs etc          

• Filter design implementations at code level

• Develop real-time embedded firmware for microcontrollers.

• Design to meet the requirements of functional safety standards.

• Troubleshooting and resolving firmware bugs, and validating functionality by testing

Requirements

• Bachelor Degree or Master’s Degree (is a plus) in Electronics and Communication or Electronics and Electrical or Instrumentation or Computer Science Engineering or Mechatronics

• Minimum 6 years of experience in Low-power electronics firmware development

• Programming language: Embedded C/C++, Assembly languages`

• Tools: IAR Workbench, Kiel IDE, SVN (Version Control)

• Operating System: RTOS

• Microprocessor architecture, peripherals, and related analog/digital circuitry.

• Software debuggers and emulators for RENESAS / TI / ARM cortex processor family.

• Setting and using lab equipment such as oscilloscopes and logic analyzers

• Knowledge of Industrial Communication Protocols: HART, Foundation Fieldbus, PROFIBUS, MODBUS

• Knowledge of distributed control systems and/or programmable logic controllers

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Role: Technical, Lead DEA  ASIC 

Job Description

This position is in Bangalore, India.

In this position, the individual will use specialized knowledge to deliver
technology solutions to develop products or solve business problems.  This
person will partner with multiple internal teams including ASIC engineering,
Information Technology, and Tools & IP Business with the goal to ensure that
flash products and ASIC projects are executed efficiently and timely with
highest quality.  We are looking for an engineer who is passionate about
providing best engineering infrastructure and design automation to ASIC
engineering community.

ESSENTIAL DUTIES AND RESPONSIBILITIES
o Critical contributor on global CAD & methodologies team for flash product
ASIC development
o Responsible for the success of high performance computing support, devtools
application support, design verification regression support, and user
environment support
o Interface with internal customers and stakeholders to identify project
requirements, scope, and priorities
o Responsible for architecting solutions such as ASIC development flow
Continuous Integration environment spanning U.S., Israel, Taiwan, and India
o Software development for design verification with emerging AI/ML and cloud
infrastructure technologies

REQUIREMENTS
o BS or MS (preferred) in Computer Science, Computer Engineering, Electrical
Engineering, or a related field
o Minimum 7 years of related experience with job scheduler, version control
systems, CI/automation, code review tools, defect tracking systems,
collaboration tools, design verification regression flows, or equivalent
o Hands-on working knowledge of Altair Accelerator, Git/BitBucket, Jenkins,
Jira, Confluence, Linux, or equivalent
o Advanced scripting skills in Python, Perl, TCL, UNIX shells, or equivalent
o Experience with Verilog, C/C++, System Verilog, Cadence/Synopsys/Mentor
verification tools
o Preferred experience with on-prem and cloud infrastructure
o Preferred experience with using public cloud providers (AWS, GCP, Azure)
o Preferred experience with container technologies like Docker and Kubernetes
o Familiar with product/software development life cycle
o Self-motivated and demonstrated ability to collaborate well with multiple
distributed teams
o Excellent written, verbal communication and interpersonal skills
o Able to multi-task, handle urgency, and meet deadlines
 

Qualifications

REQUIREMENTS
o BS or MS (preferred) in Computer Science, Computer Engineering, Electrical
Engineering, or a related field
o Minimum 7 years of related experience with job scheduler, version control
systems, CI/automation, code review tools, defect tracking systems,
collaboration tools, design verification regression flows, or equivalent
o Hands-on working knowledge of Altair Accelerator, Git/BitBucket, Jenkins,
Jira, Confluence, Linux, or equivalent
o Advanced scripting skills in Python, Perl, TCL, UNIX shells, or equivalent
o Experience with Verilog, C/C++, System Verilog, Cadence/Synopsys/Mentor
verification tools
o Preferred experience with on-prem and cloud infrastructure
o Preferred experience with using public cloud providers (AWS, GCP, Azure)
o Preferred experience with container technologies like Docker and Kubernetes
o Familiar with product/software development life cycle
o Self-motivated and demonstrated ability to collaborate well with multiple
distributed teams
o Excellent written, verbal communication and interpersonal skills
o Able to multi-task, handle urgency, and meet deadlines
 

Job-Title: STA/Synthesis
Responsibilities:
· In this position, the individual will be responsible for complete ownership of full chip  low power methodology and signoff for high performance designs, development-debug of UPF and CLP convergence and closure.
· Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.
· He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.
· The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map.
· Ability to work with minimal supervision and drive to exceed expectations is a plus.
· Hands on direct experience in Synthesis with emphasis on STA and Low Power design.
· Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must.
· The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16/7 nm designs.
· Expertise in Design Compiler is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS.
· Good verbal and written communication skills are required.

Job-Title: Block/Fullchip PNR 
Responsibilities:
- In this position, the individual will be responsible for delivering complex ASIC / SoC designs, collaborating with cross-functional teams to identify risks and contribute to the development of physical design methodologies that enable the delivery of high-quality ASICs in a timely manner.

- 10+ years of experience in ASIC/SoC Physical Design • Have solid hands-on experience with entire physical design process from floor plan till GDS generation •

-In-depth experience in Physical implementation and SoC technologies such as Floor-planning, Power Planning/Analysis, Clock Tree Synthesis Place and Route, Timing closure, and Static Timing Analysis •

-Experience with technology nodes ranging from 7nm and below nodes and ASICs with size upwards of 10M+ •

-Strong knowledge of EDA design tools like Cadence or Synopsys • Excellent communication and leadership skills with experience in people management and cross-functional interactions•

-Knowledge of Industry-leading protocols such as FLASH, PCIe is a must. •

- Have hands on experience in latest sub-micron technologies below 10 nm • Hands on experience in leading PnR tools Synopsys/Cadence. •

-Experience in low power designs and handling congestion or timing critical tiles will be preferred. • Should be a quick learner and have good attention to detail Experience in ECO implementation preferred. •

-Scripting skills in Perl/Tcl etc. • Should be able to schedule and track deliverables 

-Signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV,etc). Candidate should have worked in multiple Tapeouts

-Good verbal and written communication skills are required.

Job-Title: STA/Synthesis
Responsibilities:
· In this position, the individual will be responsible for complete ownership of full chip Synthesis /STA environment for low power, high performance designs, development-debug of interface and core side constraints, clock tree analysis and assisting full chip timing convergence and timing closure.
· Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.
· He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.
· The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map.
· Ability to work with minimal supervision and drive to exceed expectations is a plus.
· Hands on direct experience in Synthesis with emphasis on STA and Low Power design.
· Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must.
· The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16/7 nm designs.
· Expertise in Design Compiler, Prime Time and Formality  is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS.
· Good verbal and written communication skills are required.

Must have Skills:

• Strong in C Programming.
• Pre-Silicon or Post Silicon Validation, Embedded systems experience.
• Experience with emulation and prototyping platforms
• Hands on JTAG debuggers and In circuit Emulators such as Lauterbach, Digilent etc.
• Should be able to handle lab equipment like scopes, Logic analysers, dev boards etc.,
• Should be able to read and understand schematics of the hardware boards.

 Good to have Skills:

• Exposure to C++ and Python programming
• Exposure to ARM/ARC cores and its architecture
• Exposure to AMBA bus architectures like AXI/AHB/APB
• Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT
• Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies.
• Experience with Palladium(Z1 from cadence), FPGA(HAPS from Synopsis) platforms
• Exposure to identifying signals and taking wave dumps on palladium platforms, and its analysis
• Exposure to GreenHills and Niagara tools

Job Description

• Develop/execute/debug test cases in Pre-Silicon Validation on Palladium, FPGA emulators.
• Develop and port drivers and test Firmware for IP blocks for Flash(NAND) and HDD(Hard Disks) products.
• Debug failures and perform root cause analysis with JTAG Debuggers, Scopes, Logic Analysers in both pre and Post-Si environments.
• Be involved in SOC bring-up and Post Si Validation.
• Understanding the test scenarios and converting them into test cases.
• The candidate will be responsible for developing and executing extensive functional test suites using internally developed and industry standard tools to thoroughly validate IPs and SOC products.
• Candidate will be working closely with architects, designers, verification and software engineers to help validate the next generation memory devices.