Total 76 firmware engineer job vacancies in Art / Design / Entertainment category in D19 Serangoon Garden, Hougang, Sengkang, Punggol

Job Responsibilities:

· Liaise with sales team, geotechnical team and customer to collect project information

· Preparation of TBM (tunnel Boring Machine) technical offers (Design Calculations, Datasheet, Scope of supply, Method Statement, and other Supporting Documents)

· Clarification of technical requirements and technical solutions with various subsidiaries

· Order and review technical drawings with Drafting Department

· To support Herrenknecht Asia Headquarters (HAQ) sales activities of Japanese construction companies within Asia region

· Support of project manager during the execution of projects; participate in design meetings and help to prepare required technical documents.

· Assist the field service activities in Japan with required technical documents and meetings.

Job Requirements:

· At least an associate degree in Mechanical or Civil Engineering

· With 1 to 3 years of relevant working experience in the tunnelling or relevant industry

· Some experience in steel structure manufacturing or machinery fabrication would be preferred

· Possess good interpersonal and effective communication skill. An excellent team play who can also work well independently with minimum supervision and results-oriented in a fast-paced environment

· Good written and spoken Japanese to liaise with Japanese-speaking clients

· Good computer literacy skills with software, eg. Microsoft and/or windows applications

Responsibilities:

• Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout

Requirements:

• Bachelor/Master Degree in Electrical/Computer Engineer.
• Experience in physical design with tape-outs.
• Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
• Good in script programming with Perl, TCL/TK or other languages.

Responsibilities

• Advanced low-power physical design/integration flow development
• Synthesis, floor planning and place & route
• Full-chip floor planning and layout
• Power network design and analysis
• Support signoff timing closure, power integrity, and signal integrity
• Physical Verification using DRC, LVS

Qualifications

• Degree or related field required
• 3+ years industry experience required
• Experience on high performance and low-power physical design
• Experience on deep sub-micron process technology (14nm and below) taped outs
• Experience on floor planning, power network design, power optimization/analysis, clock-tree design, static-timing analysis, DRC, LVS
• Excellent interpersonal and communication skills
• Experience on using Perl, TCL, Make, and other script languages
• Experience on Synopsys or Cadence tools (Design Compiler, IC Compiler, StarRCXT, Primetime, Innovus)
• Experience on Mentor or Synopsys verification tools (Calibre, ICV)

Responsibilities

• Advanced low-power physical design/integration flow development
• Synthesis, floor planning and place & route
• Full-chip floor planning and layout
• Power network design and analysis
• Support signoff timing closure, power integrity, and signal integrity
• Physical Verification using DRC, LVS

Qualifications

• Degree or related field required
• 3+ years industry experience required
• Experience on high performance and low-power physical design
• Experience on deep sub-micron process technology (14nm and below) taped outs
• Experience on floor planning, power network design, power optimization/analysis, clock-tree design, static-timing analysis, DRC, LVS
• Excellent interpersonal and communication skills
• Experience on using Perl, TCL, Make, and other script languages
• Experience on Synopsys or Cadence tools (Design Compiler, IC Compiler, StarRCXT, Primetime, Innovus)
• Experience on Mentor or Synopsys verification tools (Calibre, ICV)

Responsibilities

• Work with IC designers and chip leads to architect, design and optimize custom layout of standard cells.
• Layout design of analog circuit blocks with attention to matching and minimizing parasitics in the layout.
• Physical Verification using DRC, ERC and LVS.

Qualifications

• BSEE or higher required
• 5+ years industry experience required
• Strong analog layout design skills
• Expert-level knowledge with Cadence Virtuoso tool suite
• Expert-level knowledge with Mentor Graphics Calibre
• Strong experience in advanced node IC layout. Knowing GAA is preferred.
• Able to work independently on challenging problems
• Understand layout considerations for device matching, coupling and noise isolation
• Excellent communication skills (both oral and written) arerequired
• Able to study custom circuit simulation/characterize library/custom circuit design for future work. Having one of those capability is preferred

• Examine Structural Drawings provided by consultants.
• Support the Design Manager in overseeing consultants during both the Tender stage and Site implementation phase.
• Conduct initial structural design analysis / conceptual design to aid in Tender costing. Aid the project and operation teams in resolving structural design challenges.
• Ensure adherence to design procedures in accordance with the OHSQ Management System.
• Plan and manage design tasks and schedules to ensure timely and accurate production and approval of shop drawings.
• Communicate with clients regarding design details of shop drawings and suggest alternatives when necessary.

Requirement:

• Minimum 5 years experiences in shop drawings preparation for large scale projects.
• Candidate must prossess Professional Engineers Board recognized Degree in Civil/Structure Engineering with relevant design working experience
• Familiar with Auto CAD software and knowledge in BIM software will be an added advantage

Reg no. R1659970

The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital design team with the aim to create an efficient Digital Design.

Responsibilities and Duties include but not limited to:

• Work at IP level design, but occasionally also at SOC design.
• Creation of RTL code
• Some opportunities to integrate the IP in the SOC
• UPF flow, Low power Flow, Power aware simulations
• CDC/RDC/LINT checks using various tools
• Verification of concept using Matlab/Simulink and toolboxes
• Synthesis, Scan insertion, ATPG.
• STA.
• Schedule preparation at IP level together with the Design leader and execution adhere to plan.
• Reporting to the management.
• Accountability.

Qualification Requirements:

• Masters in Electronics' Engineering (a relevant experience with minimum 2 years in a semiconductor or high technology R&D environment would be appreciated)
• Some Knowledge/Experience/Exposure as below would be appreciated:

1. ARM based Architectures, AMBA bus, Peripherals, Boot
2. RISC-V architectures
3. Hardware Design Language (such as VHDL or Verilog)
4. CDC, RDC, LINT
5. Synthesis, Scan Insertion, ATPG
6. Physical Design, including Power analysis, Clock tree Synthesis, Power Gating, Physical Checks
7. Power Aware, Low power and UPF methodology
8. Tools porting from Verilog RTL into C++
9. Scripting languages (PERL, TCL, PYTHON)
10. Knowledge in Static Timing Analysis

• Able to work in a multi-cultural team.
• Strong analytical and problem-solving skill.
• Able to keep up with fast moving new design methodology.
• Candidates with extensive experiences will be considered as Staff Engineers/Design Managers
• Salary package will be offered base on working experience

• Liaise with Clients, Architects & Builders.
• Recognized Degree in Civil and Structural Engineering.
• Minimum 5-8 years experience in structural design.
• Familiar with reinforced concrete and steel design.
• Responsible for design and checking of drawings.
• Coordination of project submission to authorities and construction.
• Must be willingly to work on construction sites (dusty & dirty environment), long hours and Sundays/Public Holidays (if required)
• Salary will commensurate base on qualification and experience

All candidates welcome to apply

Job Summary:

• Industry: Construction
• Working Location: Tanjong Pagar/West Coast
• Working schedule: Monday to Friday (8.30 am to 5.30 pm) + Saturday (8.30 am to 12.30 pm)

Job Responsibilities:

• Review civil and structural drawings from consultants
• Assist the Design Manager in managing the consultant during Tender stage & Site implementation phase
• Conduct preliminary structural design analysis/conceptual design for tender costing purposes.
• Assist project team and operation team in solving all structural design-related issues
• Ensure design work procedure be properly and effectively implemented accordingly to OHSQ Management System
• Manage and plan design work and schedule to ensure shop drawings are accurately produced and approved in time
• Liaising with clients on shop drawing design details and propose alternative

Job Requirements:

• Minimum 5 years experiences in shop drawings preparation for MRT or LTA road projects
• Candidate must prossess Professional Engineers Board recognized Degree in Civil/Structure Engineering with relevant design working experience
• Familiar with Auto CAD software and knowledge in BIM software will be an added advantage
• Must be a team player

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We regret that only shortlisted candidates will be notified.

Registration No: R23113834

Key responsibilities:

• Perform IC design of FTDI products
• Perform Verilog RTL design to meet product specifications and requirements
• Perform front-end verification using UV methodology
• Work with Systems and Software engineers on FPGA verification
• Perform Logic Synthesis, Static Timing Analysis
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with Physical designer to achieve timing closure
• Work with test team in debugging production test issues
• Help debug & correct any functional issues found in taped-out devices
• Participate in design reviews, support ISO processes and documentation

Additional responsibilities:

a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.

b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge and skill requirements:

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in the area of digital IC design
• Working experience from design to tape-out are essential
• Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure
• Experience in using EDA tools from Cadence, Synopsys
• Knowledge and working experience in one or more of the following:

1. Digital and mixed-signal design
2. USB interface products
3. Knowledge in connectivity technology such as USB, UART, SPI, I2C
4. Project Management

Working Conditions:

• Working conditions are normal for an office environment.
• Work requires willingness to work a flexible schedule.

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills

Company Description

Continental develops pioneering technologies and services for sustainable and connected mobility of people and their goods. Founded in 1871, the technology company offers safe, efficient, intelligent and affordable solutions for vehicles, machines, traffic and transportation. In 2022, Continental generated sales of €39.4 billion and currently employs around 200,000 people in 57 countries and markets.

The Automotive group sector comprises technologies for passive safety, brake, chassis, motion and motion control systems. Innovative solutions for assisted and automated driving, display and operating technologies, as well as audio and camera solutions for the vehicle interior, are also part of the portfolio, as is intelligent information and communication technology for the mobility services of fleet operators and commercial vehicle manufacturers. Comprehensive activities relating to connectivity technologies, vehicle electronics and high-performance computers round off the range of products and services.

Job Description

· As PCB Design Engineer you are responsible to develop PCB Designs according to project requirements including placement, routing, and panel PCB in the Business Area Architecture & Networking.

· You work together with different disciplines and competency fields.

· You are responsible for the technical specification in the field of PCB Design with consideration for quality, costs, and manufacturability.

· In detail you are in charge with:

· Perform PCB design from Schematic, Technology selection, Transfer of constraints to PCB design layout, Design creation & check and to Gerber for manufacturing.

· Creating documents and releasing outputs in product data management systems.

· Support for cross-discipline and cross-location cooperation.

· Support for acquisition projects.

· Support of competence and knowledge management.

· Design PCB in single sided, double sided & multilayer, Flex technologies and HDI.

· Collect pre-layout requirement, propose solutions, and complete checklist to ensure all disciplines have reviewed and agreed on design release.

· Provides PCB technical support, etc. Eg. answering Engineering Query from PCB fabricators.

· Manages planned schedule to ensure delivery with quality.

· Design for reliability and high-density manufacturing by applying DFM approach and following our design guideline.

Job Requirements

· University, or Bachelor in Electronic Engineering or Physics or alternatively Diploma in Electronics Engineering with at least 5 years' experience in PCB board design with 4 or more layers.

· Understanding of electrical component behaviors, knowledge of specific electrical requirements (mixed signal, high-speed digital and analog design)

· Comprehension of electrical circuits.

· Ability to identify electrical and technical parameter with influence on the PCB design.

· Communication and collaboration skills.

· Good knowledge of PCB Design Guidelines, Standards & Regulations, Printed Circuit Technologies, impedance-controlled trace, high current calculation, board and panel size management.

· Experience in using Zuken application will be added advantage.

· PCBA manufacturing process knowledge.

· Able to work independently or effectively as a team member with global team at different time zone.

Electronics Design Engineer/Assistant;

• Degree/Diploma in Electronics/Electrical Engineering.
• Minimum 5 years if extensive PCB layout experience and familiar with Altium Design Software.
• PCB layout (gerber), provide BOM, testing instruction for PCBA.
• Ability to offer alternative parts for EOL components.
• Debugging, testing of PCBA failure and provide appropriate corrective actions in meeting customers specifications.
• 5-day work week (8:00am to 5:30pm)
• Close liaison with production team on manufacturing process.
• Liaison with sub-contractor on engineering issues where applicable.
• MS office proficiency.
• Salary S$4,000 to S$5,000/- pending experience in Design & Testing capability.
• Those with less experience will start as Assistant Design Engineer (S$3,300 to S$4,000)
• Only those with relevant PCBA design experience need to apply
• Bilingual
• 5-day work-week (8:00am to 5:30pm)
• Location; Toa Payoh

Job description:

As a member of the filter design team, the successful candidate will play a key design role as a product owner of resonator/filter in development and commercialization of acoustic filters with both BAW and SAW technologies from beginning, concept meeting to end, mass production including characterization.

Experience with either SAW or BAW filter design -layout, simulation, fabrication, and characterization- is required for senior position and principal position is available for candidates with proven track record in ramping up commercialization of acoustics filters in mass production environment.

Responsibilities:

- Co-work with international team across China, Singapore, South Korea, and Europe on a cross-disciplinary team basis

- Use commercial circuit analysis and physical modelling tools as well as custom software packages to design and analyse acoustic filters

- Assist RF measurement analysis by generating test plans and analysing results

- Produce RF engineering reports to support team members

- Communicate with R&D team for co-design and device improvement

Qualifications/Desired skills:

- Track record in design and mass-production of SAW/BAW filters for mobile applications is highly desirable

- Strong skills and working knowledge of design simulation tools, e.g. ADS, AWR, HFSS, COMSOL, etc

- Understanding of RF test parameters and test equipment

- Understanding of filter application and mobile communication system and architecture

- Experience with drawing programs, schematic capture and PCB layout tools

- Experience in RFIC design, RF module and front-end system design is preferred

- Knowledge of MEMS fabrication

- Strong written and verbal English skills to support complex analysis

- Organized team player and a good learner who is open to discussions

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

Responsibilities

The chosen candidate will contribute to, and manage a team for, the development of architecture, microarchitecture, and design of complex, low power, Wireless SoCs. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML, while meeting best-in-class power and performance targets. The Chip Design lead will define architectures with embedded multi-core, multi-threaded processor subsystems, AI accelerators, bus interconnect, memory architecture and multi-level caches to satisfy performance and throughput requirements. This will include RISC-V, ARM or proprietary processor designs, high-speed interfaces for off-chip memories, integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.

• Lead the development and execution of Wireless SoC’s from definition, through execution, and into production
• Definition and Planning
  Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates.
  Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse.
  Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.
• Project Execution
  Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation.
  Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure.
  Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams.
  Follow established quality procedures and processes to achieve first tapeout.
• Validation to Production
  Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification.
  Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary

Skills You Will Need

Minimum Qualifications:

• B.Tech/M.Tech in related branches of electronics and computer science with a minimum of 10 years of related experience.
• Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
• Top-down planning and execution of SOC projects.
• Experience in full-chip development cycle
• Able to build strong technical team.
• Hands-on experience in architecture, micro-architecture, digital design processes
• Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
• Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
• Knowledge of processors like RISC-V and ARM processors
• Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
• Knowledge of DFT including Scan, ATPG, MBIST
• Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
• Knowledge of hardware accelerators
• Knowledge of Verilog and System Verilog
• Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks:

You can look forward to the following benefits:

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station