Total 209 Visual Design Director inPulau Pinang job vacancies in Art / Design / Entertainment category in D05 Clementi New Town, Hong Leong Garden, Pasir Panjang

Established in 1973 with headquarters in Seoul, South Korea, Cheil Worldwide is one of the world’s leading integrated marketing communications networks, with more than 6,800 employees globally in more than 54 offices in 46 countries.

For more information, visit us at: www.cheil.com.

We are inviting candidates for the position of:

Art Director/Senior Art Director

Responsibilities

· To generate exciting ideas to fulfil clients’ briefs and to engage in executing layout designs for art work and copy

· To supervise shoots independently locally and overseas

· Independently oversee a project cycle; from conceptual to production

· Meets art department work standards by following production, productivity, quality, and customer-service standards; resolving operational problems; identifying work process improvements

· Produces illustrative material by assigning layout design concept to artists and photographers; directing development of design concepts into art layouts

· Prepares layouts for printing by marking-up, pasting-up, and finishing layouts

· Have a positive attitude towards collaborating with team members and other stakeholders to participate in pitches

· Competent in bringing the ideas to life visually

· Ensuring a high standard of visual execution across all media and campaigns

Requirements

· Candidates should possess about 3 years of relevant experience with an integrated portfolio

· An excellent team player and to be able to work well with front-end/back-end programmers

· Possess a good eye for craft with the ability to work independently

· Good communication and presentation skills

· Strong production knowledge in TV, Print and Digital

· Experience on activation and in UI

· Experience in UX / wireframes

· Competent in Photoshop, Illustrator and InDesign

· Knowledge on other softwares: InVision, Sketch, AfterEffects, and Animate CC would be an advantage

At Cheil, we are passionate about ideas that move.

We believe that the right idea will move seamlessly across channels: from online to offline, above the line to below the line, in-store to out-of-home. It will move brands, move products and most importantly, move people. The right idea will move everything forward.

Established in 1973 with headquarters in Seoul, South Korea, Cheil Worldwide is one of the world’s leading integrated marketing communications networks, with more than 6,800 employees globally in more than 54 offices in 46 countries.

For more information, visit us at: www.cheil.com.

We are inviting candidates for the position of:

Content Publishing / Graphic Design Intern (Full-time internship)

Job description

Working with the Samsung Electronics SEA & Oceania business, you will have the privilege of working within a big data environment where strategic decisions are made, guiding best in class upholding brand compliance.

• Content Audit & Analysis: Work closely with the Content Team to conduct content audits on Samsung.com to ensure content is brand compliant and aligns with our strategic objectives.

• Progress Tracking & Reporting: Analyse, track, and report progress on weekly and monthly reports for multi-market operations, providing insights and recommendations for optimization.

• Training Document Management: Prepare and maintain training documents, Standard Operating Procedures (SOPs), and any other necessary documents to support team operations and knowledge transfer.

• Assist in Design Projects: Execute simple design tasks such as key visual adaptations for regional campaigns, ensuring alignment with brand guidelines and creative direction.

• Asset Management: Organize and maintain digital assets, including images, graphics, and other design elements, to facilitate efficient workflow and collaboration within the team.

Desired Skills and Experience

• Good skill in Excel and PPT

• Good skill in Adobe Illustrator and Photoshop

• Pursuing or recently completed a degree in Graphic Design, Visual Communication, or a related field.

• Analytical and quantitative, with strong attention to detail

• Self-starter with excellent communication and collaboration skills, with the ability to work effectively in a team environment.

• Ability to thrive in a fast-paced, ambiguous, interruptive environment

• Ability to work independently as well as work collaboratively toward a common goal

Responsibilities:

• Conduct Solution Architecture activities when required on Bids and Projects, in close collaboration with Systems Engineers and reporting to the PDA in that case. In charge of proposing Solution Compliance.
• Support the Solution Orientation Review (SOR) for Bids in collaboration with the Solution Engineering Manager (Bids), Services Engineering and assigned bid team members.
• Propose draft DVa and report to the PDA in terms of Solution definition for allocated Bids/Projects.
• Ensure that the design of the Solution satisfies:
  • Customer needs and contractual requirements for a project,
  • Contractually applicable technical standards,
  • Alignment with the Product Policy,
  • Cost effectiveness, and
  • Applicable design legislation, rules and regulations.
• Ensures, with the support of Specialty Engineering experts & HSE stakeholders that:
  • Solution design takes into account contract requirements in terms of Safety, Security and Human Factors and applicable legislation, rules & regulations, including Environmental/HSE requirements & standards,
  • Related certification activities are performed correctly.
• Particular focus on risks qualification and quantification and mitigation actions at Bid phase and follow-up at Project phase. Risks must be understood and mastered.
• Participate in specific actions plans and dedicated task forces as allocated to solve complex technical problems.
• Contribute to elaborate the TopSKY-ATC product policy through commonalising specific Solutions required by projects and support the HE Product Design Authority in maintaining a rigorous Product policy.
• Take charge of a Technical Speciality when required (e.g. Network & Infrastructure) with the aim to:
  • be the subject-matter expert within the organization,
  • provides a conduit for the sharing of state-of-the-art knowledge across the discipline,
  • be responsible for capitalisation within his/her discipline.
• Pro-actively share knowledge with the experts network inside the AMS Business Line and participate when required into external events in the technical & ATM expert fields to represent Thales AMS.

Requirement:

• Tertiary Qualifications in Engineering
• Degree in computer sciences (minimum Bachelor of Sciences) and network discipline
• 7 years minimum of experience holding positions in systems engineering and/or software engineering and/or integration on complex software-centric real-time systems.
• A proven track-record in supporting the design of Solutions for complex System Of Systems.
• Proven capability to work in a multi-cultural environment and with variety of international customers.
• Experience in the ATM Domain is mandatory.
• Language: fluent English, French would be a plus.
• International work context
• Aptitude to work effectively as part of a team.
• Resilience under pressure.
• Capacity to learn quickly.
• Capability to manage various stakeholders having different objectives.

Responsibilities:

• Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout

Requirements:

• Bachelor/Master Degree in Electrical/Computer Engineer.
• Experience in physical design with tape-outs.
• Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
• Good in script programming with Perl, TCL/TK or other languages.

Hex Trust is a fully-licensed and insured digital asset custodian. Led by veteran banking technologists and award-winning financial services experts, Hex Trust has built Hex Safe, a proprietary bank-grade platform that delivers solutions for digital asset protocols, foundations, financial institutions, and the Web3 ecosystem. Hex Trust has offices in Singapore, Hong Kong, Dubai, Italy, and Vietnam.

Position Summary

Join our team as a Design Intern and embark on an exciting journey of creativity and collaboration!

Duties & Responsibilities

• Engage in the complete design cycle, from research and ideation to execution
• Collaborate with various teams and report to the Marketing Manager
• Adhere to our brand guidelines while designing sales & marketing materials
• Create designs across diverse media based on creative briefings
• Juggle between teams and projects, adapting to varying specifications
• Familiarize with the business needs and design accordingly

• Proficiency in Adobe Creative Suite
• Exceptional organizational and communication skills
• Strong grasp of design fundamentals, layout, and typography
• Openness to constructive criticism and feedback
• Ability to work independently and lead when necessary
• Excellent problem-solving abilities and attention to detail
• Knowledge of design tools including Photoshop, After Effects, and Illustrator
• Understanding of design methodologies, user-experience/interface design, and corporate identity/branding
• Additional preference: Web design knowledge and experience in Webflow

As one of the leading Web3 innovators, Hex Trust offers a front-row seat in the ever-changing blockchain & crypto industry. We genuinely believe that people are our greatest asset, and invest heavily so they’re best prepared to support our mission to unlock ownership in decentralized markets! You will be joining a company that is always committed to creating a supportive & inclusive environment that promotes personal and professional growth that furthers your success and drives innovation, collaboration, and passion in the blockchain space.

At Hex Trust, we are proud of our R.A.P.I.D. culture:

• Respect and Inclusion
• Agile
• Passionate
• Indivisible
• Driven by integrity

Join us at Hex Trust and not only can you look forward to working with blockchain professionals to build the decentralized future, but also:

• Flexible Work Arrangements
• Professional Learning and Development Opportunities
• Elevate your work using cutting-edge technology
• Fun & friendly office spaces in Hong Kong, Singapore, Dubai and Vietnam

Hex Trust is an equal-opportunity employer devoted to diversity and inclusion in the workplace. We do not discriminate on the basis of race, religion, colour, national origin, gender, sexual orientation, age, marital status or disability status.

For more details about the responsibilities of this post please find attached links to the Job Description and Personal Specification Whilst it is not a legal requirement, Hertfordshire Community NHS Trust encourages and supports all staff to be vaccinated as this remains the best line of defence against COVID-19. We are committed to supporting flexible working options for staff, wherever possible, and welcome discussions on flexible working patterns to support our staff to maintain a healthy work life balance.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Executive Assistant to Director Planning and Environmental Services
About Us
Gunnedah Shire Council is an integral part of the Gunnedah community, a vibrant, warm and friendly town surrounded by the expansive Liverpool Plains and framed by the Kelvin Ranges. The Koala Capital of the world offers much more than just our famous furry friends! With a population of approximately 13,085 Gunnedah is a commodity hub and major destination on the intersection of the Kamilaroi Highway Touring Route and Oxley Highway. Here at Gunnedah Shire Council, we are committed to providing a friendly and helpful service to all stakeholders and a liveable and accessible community for all ages and demographics. Additionally, we are proud to promote economic and business development in the region.
It is important to note that we are not only invested in the people of Gunnedah, but also heavily invested in our employees and their future careers. 


... Click here to view more detail / apply for Executive Assistant to Director Planning and Environmental Services

• Position :Design Executive/Drafter (BIM/CAD- CIVIL/STRUCTURAL)
• Location : Near Ubi MRT
• Working hours : 5 days work week, Monday - Friday : 8.30am to 5:30pm,
• Salary (commensurate with experience) : Up to $64200 + Variable bonus+ 14 days Annual leave
• Duration : Permanent
• Industry : Building/Construction

Main Responsibilities

• Prepare and facilitate design drawings using BIM and CAD technologies for building construction.
• Liaise and coordinate with main contractor and other trades for cross-team support on BIM software.
• Ensure all models are compatible and BIM data are made available to all project participants.
• Collaborate within design team and other relevant departments to ensure all drawings are in
• order as per design requirements.
• Any other tasks as may be assigned from time to time.

Requirements

• Certificate/Diploma/Degree in Architectural / Civil Engineering or equivalent
• 1-2 years of related work experience in similar capacity for construction and architecture
• projects
• roficient in MS Office, Revit, Navisworks and AutoCAD software
• Knowledge of DGN, DWF, IFC and MicroStation
• Knowledge of native formats of BIM authoring or BIM related applications for design reviews environment

Email to joie@searchpersonnel.com.sg

Do visit Search Personnel Pte Ltd for more job listings.

***We DO NOT charge our candidates any referral fee nor bind them with any contract.***

Joie Chang

Deputy Consulting Director (APAC)

Reg no.: R2090601 | EA No: 13C6684

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills

Job Description:

- Perform Civil, Structural Analysis and Design (entry-level) to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- Reporting to Senior Engineer

Job Requirements:

- Candidate must possess at least a Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 1 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

- Candidate with longer experience or qualifications will be considered for Senior Positions

The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital design team with the aim to create an efficient Digital Design.

Responsibilities and Duties include but not limited to:

• Work at IP level design, but occasionally also at SOC design.
• Creation of RTL code
• Some opportunities to integrate the IP in the SOC
• UPF flow, Low power Flow, Power aware simulations
• CDC/RDC/LINT checks using various tools
• Verification of concept using Matlab/Simulink and toolboxes
• Synthesis, Scan insertion, ATPG.
• STA.
• Schedule preparation at IP level together with the Design leader and execution adhere to plan.
• Reporting to the management.
• Accountability.

Qualification Requirements:

• Masters in Electronics' Engineering (a relevant experience with minimum 2 years in a semiconductor or high technology R&D environment would be appreciated)
• Some Knowledge/Experience/Exposure as below would be appreciated:

1. ARM based Architectures, AMBA bus, Peripherals, Boot
2. RISC-V architectures
3. Hardware Design Language (such as VHDL or Verilog)
4. CDC, RDC, LINT
5. Synthesis, Scan Insertion, ATPG
6. Physical Design, including Power analysis, Clock tree Synthesis, Power Gating, Physical Checks
7. Power Aware, Low power and UPF methodology
8. Tools porting from Verilog RTL into C++
9. Scripting languages (PERL, TCL, PYTHON)
10. Knowledge in Static Timing Analysis

• Able to work in a multi-cultural team.
• Strong analytical and problem-solving skill.
• Able to keep up with fast moving new design methodology.
• Candidates with extensive experiences will be considered as Staff Engineers/Design Managers
• Salary package will be offered base on working experience

• Liaise with Clients, Architects & Builders.
• Recognized Degree in Civil and Structural Engineering.
• Minimum 5-8 years experience in structural design.
• Familiar with reinforced concrete and steel design.
• Responsible for design and checking of drawings.
• Coordination of project submission to authorities and construction.
• Must be willingly to work on construction sites (dusty & dirty environment), long hours and Sundays/Public Holidays (if required)
• Salary will commensurate base on qualification and experience

All candidates welcome to apply

Key responsibilities:

• Perform IC design of FTDI products
• Perform Verilog RTL design to meet product specifications and requirements
• Perform front-end verification using UV methodology
• Work with Systems and Software engineers on FPGA verification
• Perform Logic Synthesis, Static Timing Analysis
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with Physical designer to achieve timing closure
• Work with test team in debugging production test issues
• Help debug & correct any functional issues found in taped-out devices
• Participate in design reviews, support ISO processes and documentation

Additional responsibilities:

a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.

b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge and skill requirements:

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in the area of digital IC design
• Working experience from design to tape-out are essential
• Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure
• Experience in using EDA tools from Cadence, Synopsys
• Knowledge and working experience in one or more of the following:

1. Digital and mixed-signal design
2. USB interface products
3. Knowledge in connectivity technology such as USB, UART, SPI, I2C
4. Project Management

Working Conditions:

• Working conditions are normal for an office environment.
• Work requires willingness to work a flexible schedule.