Total 7 Quality Assurance Engineer job vacancies in Penang

• Machine Maintenance & Support: Manage and maintain front-line machinery such as Mounters, Dicers, Die bonders, and Wire bonders, providing critical troubleshooting support and ensuring smooth operations during significant downtimes.
• Operational Efficiency: Constantly monitor and optimize Overall Equipment Effectiveness (OEE) to ensure peak performance and identify potential improvements.
• Project Leadership: The project aims to enhance machinery performance and stability through effective problem-solving methodologies, ensuring initiatives align with business objectives and yield tangible benefits.
• Cross-Functional Collaboration: Work closely with the production, process, and PC departments to implement a comprehensive preventive maintenance program that minimizes disruptions and maximizes machine reliability.

• Machine Maintenance & Support: Manage and maintain front-line machinery such as Mounters, Dicers, Die bonders, and Wire bonders, providing critical troubleshooting support and ensuring smooth operations during significant downtimes.
• Operational Efficiency: Constantly monitor and optimize Overall Equipment Effectiveness (OEE) to ensure peak performance and identify potential improvements.
• Project Leadership: The project aims to enhance machinery performance and stability through effective problem-solving methodologies, ensuring initiatives align with business objectives and yield tangible benefits.
• Cross-Functional Collaboration: Work closely with the production, process, and PC departments to implement a comprehensive preventive maintenance program that minimizes disruptions and maximizes machine reliability.

Job  Responsibility:

• Process Engineering at Assembly Process
• Setup of new product which consist of document preparation to meet IATF requirements.
• Yield & quality improvement on assigned product types / process.
• Cost reduction projects in Assembly process in order to reduce overall product cost.
• To carry out investigation & propose corrective actions related to quality issue.
• To support Production delivery

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.