Total 168 Purchasing Engineer job vacancies in The United States of America

In this position, the individual will be responsible for Designing, implementing, debugging firmware for the next generation storage devices (SD, USB, SATA).

Typical activities involve the design and implementation of data structures, software algorithms, data path, and implementation of storage interface protocols, such as UFS, to deliver future cutting-edge storage products.

You will develop firmware using multiple environments that include SW simulations, FPGA boards, and of course the final product HW. You will work in an Agile environment with advanced CI tools and capabilities that help develop clean code fast.

You will work closely with excellent colleague engineers in Israel and India, cope with complex challenges, innovate, and develop products sold to leading mobile and automotive OEMs for millions of devices across the globe.

• Understanding system specifications, Firmware and memory requirements 

• Understanding on NAND  firmware architecture and algorithms  

• Coming up with creative scenarios, test design, development, implementation and deployment.

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  Making sure firmware meets the quality and performance specifications of the product. 

• Leads  reviews with all the program members to update or changes quality standards when necessary 

Job Description:

Responsibilities:
 In this position, the individual will be responsible for complete ownership of full chip Synthesis /STA environment for low power, high performance designs, development-debug of interface and core side constraints, clock tree analysis and assisting full chip timing convergence and timing closure.
 Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.
 He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.
 The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map.
 Ability to work with minimal supervision and drive to exceed expectations is a plus.
 Hands on direct experience in Synthesis with emphasis on STA and Low Power design.
 Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must.
 The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16/7 nm designs.
 Expertise in Design Compiler is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS.
 Good verbal and written communication skills are required.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Plans, executes facilities infrastructure operating and maintenance, assisting Facilities Managers to unsure of stable utilities supply per plant requirements as well as proper periodically maintenance, monitoring of utilities supply quality ensure the utilities are adequate and qualified for production without production interruption and safety accident.
• Plans, executes facilities infrastructure projects to ensure the utilities are adequate and qualified for production without production interruption and safety accident.
• Performs technical support activities with engineering approaches and effective respond in term of productivity, quality, delivery and cost.
• Planning the capacity of facility supply by referring with the MFG demand which moving forwards to rolling plan.
• Established accurate and appropriate performance report.
• Coordinate with other sections including oversee organization concerning technical issues related to work.
• Develop the documentation related to facilities engineering and design/standards.
• Responding appropriately to emergencies or urgent issues as they arise.
• Performs related work as assigned.
• Responding facilities system reliability improvement.
• Responding new technology/innovation for fulfill facilities system (Including energy conservation)

Job Description

ESSENTIAL DUTIES AND RESPONSIBILITIES:

Staff Engineer, for Development Engineering (Process Characterization), is responsible for overall project management in identifying and quantifying all significant sources of process variation inherent to the technology and materials as applied to product design. The job will entail cross-functional work as you will be working with each individual process owner in areas such as Slider, HGA, and Test development for next next-generation Head Technology

All projects will be aligned based on the Back End Technology roadmap, wherein all technology on each process is defined based on the Wafer Design and Product Timeline.  The handling of each experimental DOE, Process Validation is done through;

• Active and proactive collaborations process development, program and drive teams to provide backend solution to tackle technical challenges in new generation products, delivering performance, quality and yield.
• Conduct experiments together with process owners and provide recommendations such as parameter set up, process instruction and actions to be taken in case of abnormalities.
• Data consolidation, summary + recommendation/conclusion and perform data analysis (including root cause analysis, as needed).
• Work on data collection and analysis using statistical software.

Job Description

ESSENTIAL DUTIES AND RESPONSIBILITIES:

Staff Engineer, for Development Engineering (Process Characterization), is responsible for overall project management in identifying and quantifying all significant sources of process variation inherent to the technology and materials as applied to product design. The job will entail cross-functional work as you will be working with each individual process owner in areas such as Slider, HGA, and Test development for next next-generation Head of Technology

All projects will be aligned based on the Back End Technology roadmap, wherein all technology on each process is defined based on the Wafer Design and Product Timeline.  The handling of each experimental DOE, Process Validation is done through;

• Active and proactive collaborations process development, program and drive teams to provide backend solution to tackle technical challenges in new generation products, delivering performance, quality, and yield.
• Conduct experiments together with process owners and provide recommendations such as parameter setup, process instruction and actions to be taken in case of abnormalities.
• Data consolidation, summary + recommendation/conclusion and perform data analysis (including root cause analysis, as needed).
• Work on data collection and analysis using statistical software.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

Principal Engineer, for Development Engineering (Process Characterization), is responsible for overall project management in identifying and quantifying all significant sources of process variation inherent to the technology and materials as applied to product design. The job will entail cross-functional work as you will be working with each individual process owner in areas such as Slider, HGA, and Test development for next next-generation Head Technology

All projects will be aligned based on the Back End Technology roadmap, wherein all technology on each process is defined based on the Wafer Design and Product Timeline.  The handling of each experimental DOE, Process Validation is done through.

• Active and proactive collaborations process development, program and drive teams to provide backend solution to tackle technical challenges in new generation products, delivering performance, quality and yield.
• Prompt feedback and correlate study with the team solutions to eradicate issues.
• Data consolidation, summary + recommendation/conclusion and perform data analysis (including root cause analysis, as needed).
• Work on data collection and analysis using statistical software. Design, build, optimize, and validate custom data acquisition systems.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• To develop and control the part quality improvement at supplier site.
• To decrease the defective parts rate to meet section's quality target.
• To establish the quality document and support to production process for component problem solving
• Drive corrective action of suppliers to recover from quality deficiencies and sustain high level of Quality
• Follow up for closure of Failure Analysis at suppliers
• Issuance of Corrective Action Request or CA Notification records in WD system on known quality issue
• Review of suppliers's performance Dashboard data. Initiate corrective action where necessary

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Develop and qualify Assembly processes that meet KPI/PCRT requirements.
• Collaborate with Design Engineering on assembly DFMEA/ PFMEA and specification requirements.
• Develop process documents (PMP, Process Control, Process instruction and OCAP).
• Develop and characterize HDA/HSA process for all new products and improve all mechanical parameters and KPI.
• Develop process parametric data to detect signal and develop system to monitor process and tools performance.
• Monitor, track and analyze process parametric data to determine process and tools capability
• Qualify process, tooling/equipment & materials and recommend design concepts to best utilize equipment and improve the process.
• Perform failure analysis and provide corrective actions and discuss with cross functional teams to resolve process tooling/equipment issues that affects the KPI performance.
• Participate in design reviews, including tolerance study, with designer and collaborate for required HDA features, keep-out zones and specification to enable for robust and capable process.
• Establish assembly process strategy prior product starts to have process control and eliminate known issue

ESSENTIAL DUTIES AND RESPONSIBILITIES:

·       To work with Cross Functional Teams and effectively deploy IATF 16949 QMS requirements.

·       QMS certification like Lead Auditor or Internal Auditor in ISO 9001 / IATF 16949

·       Good communication and Interpersonal skills is a must.

·       Should be a Team player and able to work with Global teams

·       Should have good knowledge and understanding in QMS Systems and should be able to upgrade, monitor and review the relevant QMS documents procedures,

·       Should have good knowledge in Jira programming

·       Knowledge in Software Quality Assurance is required

·       Experience in CMMI / ASPICE implementation is required

·       Semiconductor Experience in Product development / Manufacturing is required.

·       Writing & implementing the products development / integration / testing procedures (PLC / SDLC processes).

·       Preparing and presenting periodical quality reports to the management.

·       Good familiarity with other ISO standards like ISO 2015

·       Experience in Quality Domain around 14 years is preferred

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Responsible Contamination of Component Cleanliness control, reviewing cleanliness data and follow up action to be closed on any triggering and pending items.
• Provide continue improvement, best in class recipe for all critical builds of new program including improvement plan in case contamination issue or related
• Responsible for out of control plan of cleanliness both in process and components incoming
• In process source hunting & incase new program failure uptick trend, performing source hunting and DOE for contamination improvement. In addition, supporting of contamination related issue at backend error code or reliability test
• Supporting for other assignment jobs e.g. work with DAS lab/Chem-I for data correction and specification review or OCAP flow etc.  

• Minimum 6+ years of experience in Verification of IP/Sub-system/SoC holding BE(or equalent) degree or Above.
• Prior experience in working with any serial protocol verification like UFS/PCIe/SATA/USB etc.
• Experience on AMBA protocols(AXI/AHB/APB) is must.
• Strong hands on experience in Verilog, System verilog and UVM.
• UVM testbench development to build a robust, scalable and efficient testbench.
• Good expertize in C language for SOC verification and Handshake between C and SV.
• Experience in Integrating 3rd Party VIPs in Testbench.
• Hands on experience on ARM based SOC verification.
• Understand design & Arch Spec and prepare detailed verification strategy and test plan/Coverage plan.
• Good expertize in verification process from Spec to Verification Sign-off.
• Strong debugging skills to root cause the issues.
• Experience in working on Formal verification, GLS & UPF simulations.
• Good at using simulation tools like Simvision, IMC, Verdi, VCS etc.
• Good at Perl/Phython Scripting languages.
• Excellent verbal and written communications skills.

• Bachelors or Masters in Electronics/Electrical Engineering
• Minimum 10+yrs of experience in ASIC/IP Digital Design for large SOCs
• Expertise in implementation of RTL in Verilog/SV for complex designs with multiple clock domains
• Expertise with various bus matrices on AHB, AXI and NOC designs
• Working knowledge of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
• Experience in ARM processor and/or NAND Flash subsystems would be a plus
• Experience in low power design methodology and clock domain crossing designs
• Experience in Spyglass Lint/CDC checks, report analysis and signoff
• Experience in Synthesis using DC, timing analysis and closure would be a plus
• Experience of UPF flow, defining constraints working with PD teams
• Expertise in Perl, Python, TCL language is a plus
• Ability to ramp-up quickly and work cohesively with Verification/Validation teams
• Must have a good attitude and be solution-oriented
• Excellent written and verbal communication skills

• Bachelors or Masters in Electronics/Electrical Engineering
• Minimum 10+yrs of experience in ASIC/IP Digital Design for large SOCs
• Expertise in implementation of RTL in Verilog/SV for complex designs with multiple clock domains
• Expertise with various bus matrices on AHB, AXI and NOC designs
• Working knowledge of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
• Experience in ARM processor and/or NAND Flash subsystems would be a plus
• Experience in low power design methodology and clock domain crossing designs
• Experience in Spyglass Lint/CDC checks, report analysis and signoff
• Experience in Synthesis using DC, timing analysis and closure would be a plus
• Experience of UPF flow, defining constraints working with PD teams
• Expertise in Perl, Python, TCL language is a plus
• Ability to ramp-up quickly and work cohesively with Verification/Validation teams
• Must have a good attitude and be solution-oriented
• Excellent written and verbal communication skills

Technical Skills :

Platform                      :  Pre-silicon environments like FPGA, Palladium.

Languages                  :  C/C++ programming.

Protocol                      : SATA/SAS, AXI, AHB, APB, I2C, SPI, UART.

Scripts                         : Python, Perl, TCL.

Processor                   : Hand on ARM Base SoC/ASIC Validation

Responsibilities

• Develop Validation firmware using C/C++ in multiple environments using latest standards: FPGA, Simulator, for NAND/eHDD (Enterprise Hard Disk Drive) products.

  Become the subject matter expert, owner of one or more components and provide technical leadership.

  Understand the architecture and design. Come up with validation plan and execute to completion.

  You'll be leading the validation team and will be responsible for Validation firmware architecture, development and validation for enterprise products. This includes innovation, design, implementation and debug of data path, drivers needed for our large and complex validation FW environment.

  Deliver on cutting-edge storage products with interfaces like UFS, SATA,SAS etc.

  Work with cross functional teams to validate ASIC for HDD products.

  Self-motivated to work both unsupervised and as part of an agile team. Collaborate to develop self and others within group.

  Participate in planning and coordinating significant technical investigations from problem statement to conclusions.

  Understand end to end product use cases.