Total 9 design intern job vacancies in Bayan Baru

Key Responsibilities:

• Design and develop electronic hardware for IoT products across a wide range of industries.
• Utilize ECAD tools to design electronic hardware Schematic and PCB layout.
• Follow industry-standard best practices for Signal Integrity, Power Integrity and EMI mitigation.
• Take detail measurements of hardware using electrical measurement tool including but not limited to multi-meters, oscilloscopes and power analysers to assess circuit performance and design improvements.
• Demonstrate problem-solving skills in PCBA troubleshooting of typical issues encountered within the product development cycle.
• Collaborate with a team of other digital, analogue, firmware, software and mechanical design engineers to review and improve hardware designs.
• Maintain hardware design and development documentation and ensure successful production releases.

Requirements:

• Bachelor Degree in Electronics/Mechatronics Engineering or other equivalent engineering disciplines.
• Min 2 year experiences in IoT and Embedded System hardware design and development.
• Experience in using Altium Designer or other equivalent ECAD tools.
• Work independently with minimum supervision.

Perks & Benefits

• Good Career Advancement & Training Opportunities.
• Excellent Benefits - Medical, Dental, Optical, Insurance.

主要責任：

• 為各行各業的物聯網產品設計和開發電子硬體。
• 利用ECAD工具設計電子硬體原理圖和PCB佈局。
• 遵循訊號完整性、電源完整性和 EMI 緩解的業界標準最佳實務。
• 使用電氣測量工具（包括但不限於萬用電表、示波器和功率分析儀）對硬體進行詳細測量，以評估電路性能和設計改進。
• 展示解決產品開發週期中遇到的典型問題的 PCBA 故障排除技巧。
• 與其他數位、類比、韌體、軟體和機械設計工程師團隊合作，審查和改進硬體設計。
• 維護硬體設計和開發文件並確保成功的生產發布。

要求：

• 電子/機電工程或其他同等工程學科學士學位。
• 至少 2 年物聯網和嵌入式系統硬體設計和開發經驗。
• 具有使用 Altium Designer 或其他等效 ECAD 工具的經驗。
• 在最少的監督下獨立工作。

津貼和福利

• 良好的職業發展和培訓機會。
• 卓越的福利 - 醫療、牙科、光學、保險。

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

BROAD FUNCTIONS:

• Ensure smooth process transfer from GO R&D to Penang
• HAMR (CE) program development in Penang
• Manufacturing improvement projects
• Product improvement iteration qualification

Regular

• Ensure new product/process transfer from GO to Penang and develop with good process control and good reliability performance
• HAMR (CE) program development to meet the performance requirement from HDD.
• Establish unique process HAMR from NPI to mass production, throughput improvement, cost reduction, yield improvement and utilization improvement projects, & ensure no compromise in term of product quality.
• Correspond to process design change iteration for performance improvement, this includes process optimization and tribology qualification.
• Provide general guidance to sputter ME yield/process team on Magnetic & Interface related process/yield issues

Irregular

• Support inter-department projects (Back End, TEST)
• Support HDD return failure analysis sure

BROAD FUNCTIONS:

• Ensure smooth process transfer from GO R&D to Penang
• HAMR (CE) program development in Penang
• Manufacturing improvement projects
• Product improvement iteration qualification

Regular

• Ensure new product/process transfer from GO to Penang and develop with good process control and good reliability performance
• HAMR (CE) program development to meet the performance requirement from HDD.
• Establish unique process HAMR from NPI to mass production, throughput improvement, cost reduction, yield improvement and utilization improvement projects, & ensure no compromise in term of product quality.
• Correspond to process design change iteration for performance improvement, this includes process optimization and tribology qualification.
• Provide general guidance to sputter ME yield/process team on Magnetic & Interface related process/yield issues

Irregular

• Support inter-department projects (Back End, TEST)
• Support HDD return failure analysis sure

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