Total 4 infrastructure engineer job vacancies in Art / Design / Entertainment category in penang

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.