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Job Description
Memory subsystem (memory controller, system cache) and interconnect (on-chip and cross-chip) architecture design for Smart Phone, Automotive, High-performance Computing, or Data Center
System-level SW/HW behavioral power/performance analysis/optimization focusing on interplays between compute system (CPU/GPU/NPU/DSP/etc.) and memory system
Memory subsystem performance/power profiling, modeling, and competitive analysis
Requirement
Minimum Qualifications
Master's degree in Electrical Engineering or Computer Science or equivalent practical experience
Experience using SystemC/Verilog/VHDL or C/C++/Python
Knowledge of cache, memory, interconnect background, system design, and modeling tools
Preferred Qualifications
Experience with architectural design/optimization of memory hierarchy (including SRAM and LPDDR/GDDR/HBM) or interconnect (NoC, PCIe, etc.) is a plus.
Experience with performance/power profiling in using micro-benchmarking and various profiling tools is a plus
Understanding of AMBA (AXI/ACE/CHI) and industry standards (UCIe/CXL) is a plus
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