Total 4 job vacancies by Starfive International Pte. Ltd.

StarFive is a leading provider of RISC-V processors, platforms and solutions. StarFive products are widely used in smart home appliances, smart monitoring, industrial robots, traffic management, intelligent logistics, wearable devices, solid state storage, network communications and edge computing, etc.

We are intensively designing next generation high performance RISC-V CPU and RISC-V-based SoC chips. Talents who are passionate in research and development for future chips are welcomed to join us. Being part of this vibrant team, you can produce world class successful commercial chips supported by efficient software stacks.

Responsibilities：

• Design, implement and improve RTL modules using SystemVerilog.
• Translate design requirements into microarchitecture specifications and clean, synthesizable, timing-friendly RTL, including: the design of multi-stage pipelines, finite state machines, and interfaces to vendor-specific high-performance SRAM libraries.
• Maintain clear design documentation, including interface definitions, design assumptions, pipeline timing diagrams, register transitions and other details.
• Own functional modules throughout the development cycle. Responsibilities of an RTL module owner includes: Work closely with architects to refine design specifications and evaluate performance, power, and area trade-offs. Work closely with verification engineers to define test plans, debug failures, improve functional coverage and fix functional bugs. Work closely with backend engineers to improve the physical design feasibility, including lint, synthesis, and balance timing/area/power goals.

Qualification：

• BS/MS with course work in Electrical Engineering/Computer Architecture/Systems Engineering/Software Development
• Having basic knowledge of modern processor microarchitecture
• Strong knowledge of digital design fundamentals, such as combinational and sequential logic, truth tables, finite state machines, setup/hold time of flip-flops
• Proficient in SystemVerilog for RTL design.
• Experience with in C/C++ and scripting languages (Perl/Python) is a plus
• Comfortable working in Linux server environment
• Fresh Graduates are welcomed
• Strong interpersonal skills, written and oral; good team player
• Curiosity to learn and execute at a fast pace; communicate effectively with mentors and other team members

StarFive is a leading provider of RISCV processors, platforms and solutions. StarFive products are widely used in smart home appliances, smart monitoring, industrial robots, traffic management, intelligent logistics, wearable devices, solid state storage, network communications and edge computing, etc.

We are intensively designing next generation high performance RISC-V CPU and RISC-V-based SoC chips. Talents who are passionate in research and development for future chips are welcomed to join us. Being part of this vibrant team, you can produce world class successful commercial chips supported by efficient software stacks.

Responsibilities：

• Maintain the automation of development environment (CI testing) and integrate the performance modelling and simulation platform and framework for micro-architecture explorations
• Investigate the current state of the art of CPUs and system on chip architecture including cache, on-chip interconnect, and memory hierarchy
• Implement simulation models for performance modelling of System-on-Chip components like caches, interconnect, and memory controllers
• Maintain, porting and cross-compile the benchmarks and master the sampling and trace-based simulation techniques
• Join the activity of micro-architectural exploration and data analysis for different benchmarks a
• Join the activity of architecture optimization for next generation of processor
• Develop automation strategies to maintain our core performance simulation models with strict quality gating and high-quality data reporting

Qualification：

• BS/MS with course work in Computer Architecture/Systems Engineering/Software Development
• Familiarity with software development and integration; usage of tools like JIRA, GIT, GERRIT, JENKINS
• Ability to setup benchmark suite (eg: Geekbench, SPEC), profile and gather performance results
• Having basic knowledge of modern processor architecture and cross-compilation environment (e.g. embedded system development)
• Able to program with assembly languages to enable benchmark porting and debugging
• Competent in C/C++ and scripting languages (Perl/Python)
• Skillful on working in Linux server environment
• Fresh Graduates are welcome
• Strong interpersonal skills, written and oral; good team player
• Curiosity to learn and execute at fast pace; communicate effectively with mentors and other team members

Role Overview

You will be responsible for defining the next generation of high-performance, energy-efficient processor cores. You will bridge the gap between architectural intent and RTL implementation, driving the ISA extensions and microarchitectural features that differentiate our silicon. This role requires a deep understanding of pipeline design, memory hierarchy, and the evolving RISC-V ecosystem.

Key Responsibilities

• Microarchitecture Definition: Define and document detailed microarchitectural specifications for high-performance RISC-V cores, including fetch units, branch predictors, execution units, and complex memory subsystems.
• Performance Modelling: Develop and maintain performance models in C/C++ to explore microarchitecture impact on CPU performance.
• Performance Analysis: Utilize techniques like RTL simulation, performance modelling, hardware performance monitor (HPM) to identify bottlenecks in the pipeline and suggest architectural improvements.
• ISA Extension & Customization: Propose microarchitecture design for standard RISC-V ISA extension (e.g. Vector, Crypto, Bitmanip) and for customized instructions to meet the needs of customers.

Required Technical Skills

• Instruction Set Architecture (ISA): Knowledge of the RISC-V ISA and experience with privilege levels (Machine, Supervisor, User). Knowledge of ARM Aarch ISA is a plus.
• CPU Microarchitecture: Deep understanding of modern CPU techniques: out-of-order execution, register renaming, superscalar pipelines, and speculative execution.
• Modeling & Languages:
• Deep experience with C/C++
• Scripting proficiency in Python or Bash for automation and data analysis.

Preferred Skills and Experiences

• AI-Assisted Workflow: Experience with LLM-assisted coding (vibe coding) and/or AI-agent-assisted workflow automation.
• Linux OS: Deep understanding of Linux system calls. Experiences with Linux kernel modules or device drivers.
• Low-level Systems: Experience with Linux kernel boot flow on RISC-V or firmware development (OpenSBI/U-Boot).
• Verilog/System Verilog: Experience in RTL development with Verilog/System Verilog.

Education & Experience

• BS/MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Work experience of CPU architect or RTL designer is a plus.

Role Overview

You will be responsible for defining the next generation of high-performance, energy-efficient processor cores. You will bridge the gap between architectural intent and RTL implementation, driving the ISA extensions and microarchitectural features that differentiate our silicon. This role requires a deep understanding of pipeline design, memory hierarchy, and the evolving RISC-V ecosystem.

Key Responsibilities

• Microarchitecture Definition: Define and document detailed microarchitectural specifications for high-performance RISC-V cores, including fetch units, branch predictors, execution units, and complex memory subsystems.
• Performance Modelling: Develop and maintain performance models in C/C++ to explore microarchitecture impact on CPU performance.
• Performance Analysis: Utilize techniques like RTL simulation, performance modelling, hardware performance monitor (HPM) to identify bottlenecks in the pipeline and suggest architectural improvements.
• ISA Extension & Customization: Propose microarchitecture design for standard RISC-V ISA extension (e.g. Vector, Crypto, Bitmanip) and for customized instructions to meet the needs of customers.

Required Technical Skills

• Instruction Set Architecture (ISA): Knowledge of the RISC-V ISA and experience with privilege levels (Machine, Supervisor, User). Knowledge of ARM Aarch ISA is a plus.
• CPU Microarchitecture: Deep understanding of modern CPU techniques: out-of-order execution, register renaming, superscalar pipelines, and speculative execution.
• Modeling & Languages:
• Deep experience with C/C++
• Scripting proficiency in Python or Bash for automation and data analysis.

Preferred Skills and Experiences

• AI-Assisted Workflow: Experience with LLM-assisted coding (vibe coding) and/or AI-agent-assisted workflow automation.
• Linux OS: Deep understanding of Linux system calls. Experiences with Linux kernel modules or device drivers.
• Low-level Systems: Experience with Linux kernel boot flow on RISC-V or firmware development (OpenSBI/U-Boot).
• Verilog/System Verilog: Experience in RTL development with Verilog/System Verilog.

Education & Experience

• BS/MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Work experience of CPU architect or RTL designer is a plus.