Total 3 job vacancies by Qualcomm Global Trading Pte. Ltd.

Responsibilities:

Responsibilities for this position involve working closely with SOC Design, SW/System, and Chipset PE/PM/PdM to validate Digital SOC chip on ATE, SLT and Bench; collaborate with Test Engineering, SLT, and Bench to develop HVM Test Solution. The role is expected from project planning to execution on Digital SOC development. Cross collaboration work is expected with SW, System, Design, Process and Customer Engineering on power and performance related tests for High Volume Manufacturing. The individuals selected for the positions will need to be able to work in a fast paced and dynamic environment and be passionate about delivering quality work.

Requirements:

Experience in Digital SOC development from planning, silicon validation to High Volume Manufacturing phase. Experience in ATE/SLT test coverage, test HW development, data analytics/ statistics, product reliability qualification (ESD/LU, HTOL and Package Qual), ATE System correlation for power and performance, project updates to upper management and cross functional teams, stakeholder management, and risk management.

Education Requirements:

Min 3 years of related job experience in product, test, product engineering.

Bachelor's/Master’s, Electrical and Electronic Engineering or Computer Engineering 

Job Overview

Major Responsibilities: Engineer will be responsible for characterization and developing cost-effective manufacturing test solution for leading‑edge Qualcomm SoC products using advanced ATE platforms. Engineer will be developing Characterization and Test Plans, test hardware requirement documents, ATE tests/routines/programs to execute test plans, driving first silicon debug to qualify designs fabricated at external foundries, performing technical data analysis of parametric performance, driving failure analysis to completion, analyzing high volume manufacturing yields and driving test time reduction, and innovating on new test solution. Engineer will be working with IC design, system engineering, DFT/DV engineering, and Hardware applications engineering in a time critical environment across the globe. The individual selected for the position, needs to be proactive, able to work in a fast-paced dynamic environment independently, and committed on delivering quality work.

Minimum Qualifications

Bachelor's degree (or higher) in Engineering, Information Systems, Computer Science, or related field. At least 8+ years of related work experience.

Preferred Qualifications

- 3-8+ years of Test Engineering or related work experience.

- 1+ year in a technical leadership role with or without direct reports.

- Strong and hands-on ATE knowledge (Advantest 93K ATE is preferred).

- Experience in developing ATE SOC program from NPI stage to volume ramp stage and driving yield and test time reduction.

- Solid understanding in semiconductor Structural (Scan and Memory BIST) and functional testing. Good understanding of eletronics engineering fundamental. Basic knowledge on CPU, DSP, GPU will be a plus.

- Experience in one or more chiplet‑based or multi‑die products, including die‑to‑die (D2D) interfaces and associated test and yield challenges is a plus

- Knowledge and hands on experience with statistical analysis software package and techniques, quality and reliability testing.

- Experience in using collaboration tools such as GIT, SVN and JIRA.

- Strong software skills (Java, C/C++, Visual Basic, Perl, Python etc.) for programming and debugging test codes.

- Strong verbal and written communications skills. Able to organize effectively and document work thoroughly while working with local and remote teams. Has a moderate amount of influence over key organizational decisions.

Educational Requirements

Required: Bachelor's, Electrical Engineering or equivalent experience Preferred: Master's, Electrical Engineering or equivalent experience

Job Responsibilities:

• Provide FA support on customer failures by using various FA tools & techniques include non-destructive analysis, EFI (electrical fault isolation) and PFA (physical failure analysis).
• Communicate and work closely with cross-functional teams include Product Test Engineering , RMA engineering for failure verification/validation, test set up and/or test characterization.
• Perform EFI by using techniques of emission & laser stimulation, which include the Thermal emission, Photon emission, Obirch/TIVA, Dynamic Laser Stimulation and so on.
• Perform PFA include both package and silicon die level analysis by using CSAM, X-ray, sample preparation, SEM/EDX, FIB etc.
• Correlate the EFI and PFA results electrically by GDS layout and schematic study.
• Compile FA images, data into final FA report and communicate with requestors/customers.
• Participate in new FA techniques/methodologies/recipes development and tool’s evaluation projects.

Job Requirements:

• Degree in IC Design. /Electrical Computer/Material Science/Mechanical or equivalent.
• FA experience in the semiconductor industry will be preferred.
• Advantage if familiar with semiconductor fabrication, Test, Assembly & Packaging process.
• Fast for learning and able to perform independent work.
• Good communication skill and team work spirit.